Power gating for ultra-low voltage nanometer ICs

Abstract

A novel power gating (PG) structure using series-connected low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> power switches has been developed to extend the PG structure to the ultra-low voltage region while keeping low leakage power in sleep mode. The series-connected low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> power switches induce a short wake-up time due to fast current discharge through the switches, whereas the PG structure can suffer from large gate tunneling leakage currents and wake-up rush-currents. Therefore, in this paper, extra circuitries are added to control the gate-tunneling leakage and rush-currents; however the total PG switch size of the proposed PG structure including the extra circuits is the same as the conventional one. The simulation results are compared to those of other well-known PG schemes and show that, in the ultra-low voltage region, the other high-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> based PG schemes cannot be used due to the impractical delay increase and long wake-up time, whereas the proposed PG structure keeps balance among the critical PG issues. The proposed PG is evaluated using inverter chains and ISCAS85 benchmark circuits at 0.6V supply voltage which are designed using 45 nm CMOS predictive technology model.