Abstract
A power electronic converter based transmission line emulator (TLE) is presented in this paper. The TLE can emulate medium and long lines in steady-state and symmetrical faults occurring at any point in the line. A traveling wave based numerical scheme for the emulation of the line is identified and then implemented on a novel digital architecture in the field-programmable gate array part of a system on chip platform. The proposed architecture meets the real-time computation constraints through parallel processing and optimal use of hardware resources (DSP slices, block RAMs, etc.). A comprehensive analysis to determine the two important parameters of the TLE-the power converter switching frequency and observer update period while satisfying a number of constraints coming from the numerical scheme, power, and embedded hardware-has been presented. Finally, relevant simulation and experimental results on a developed 400-V 15-kVA TLE prototype have been presented for validation.
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