Power efficient voltage controlled oscillator design in 180nm CMOS technology

Abstract

In this paper, four different single ended delay cells based ring oscillators have been presented. Output frequencies of ring oscillators have been controlled by varying the supply voltage 1.4V to 3.0V. The active load concept has been used in proposed circuits. First design shows frequency variation in the range [4.50–1.40] GHz with phase noise −87.79dBc/Hz @1MHz in saturated load. Second design shows frequency variation of [6.26–2.85] GHz with pseudo-NMOS logic. Third design shows frequency variation in the range [4.54–0.77] GHz with phase noise −85.38dBc/Hz @1MHz and tuning range of 141.8% in unsaturated load. Fourth design shows frequency variation of [2.66–2.38] GHz with linear load. Simulations have been performed using SPICE based on 180nm CMOS technology at 1.8V. The proposed designs of 3-Stage, 5-Stage, 7-Stage have been compared with previous work for frequency and power consumption, phase noise, tuning range. Proposed methods show the improvement with low power consumption, low phase noise and wide tuning range.