Power efficient polyphase comb decimation filters for ΣΔ modulators in multi-rate digital receivers

Abstract

In multi-rate digital receivers, Analog to Digital Converter (ADC) mostly works at a fixed sampling rate. Subsequently, a Sample Rate Conversion (SRC) process should be executed after the ADC to extract the desired baud rate. A polyphase decomposition comb filter is widely used as a first decimation stage in SRC circuit. In this paper, a power efficient clock/data distribution technique for the input registers of the polyphase decomposition comb filter is introduced. A general form of the proposed technique is developed with respect to the filter decimation factor. An FPGA implementation for both modified and conventional polyphase comb filters is presented using Xilinx Spartan3 low power FPGA family. Implementation results show that, the proposed technique significantly reduces the overall dynamic power consumption of the polyphase comb filter up to 51.3 % and 47%, for second and third order filters respectively, depending on the decimation factor. For particular power consumption, higher input sampling frequencies is achieved by applying the proposed technique. That, in turns, improves the SNR of a second order ΣΔ modulator up to 14.82 dB and 12.4 dB, using second and third order modified filters, respectively, depending on the decimation factor.