Abstract
The electrical motion of the heart is characterised by the ECG signal. ECG elucidation can be used to detect the heart syndrome. This technology has an efficient diagnostic tool, due to the high regard of portable electronic products, low power system has fascinated more consideration in recent years. This work presents digital ECG data acquisition system to diminish the power consumption. In the proposed work, analogue block is not used, they convert the input voltage into a digital code by delay lines. This digital architecture is capable of operating with a low supply voltage such as 0.3 V and 0.1 V. In this architecture, analogue blocks such as low-noise amplifier (LNA) and filters are not used. A digital feedback loop is employed to cancel the impact of the dc offset on the circuit, which eliminates the requirements for coupling capacitors. The circuit is implemented in 130 nm and 65 nm CMOS process. The simulation results illustrate that the front-end circuit of digital architecture for 130 nm consumes 18.9 pW and 65 nm consumes 109 pW of power.
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