Power Efficiency and Delay Tradeoff of 100G Energy Efficient Ethernet Protocol

Abstract

This paper investigates the dual-mode power-saving strategy designed for the 100G Energy Efficient Ethernet. The process of this strategy is a sequence of cycles, where each cycle is an interval elapsed between two consecutive instants when the buffer of the Ethernet interface becomes empty. In each cycle, the interface first enters the fast-wake mode to perform the conditional sleep-mode selection of the strategy. If the number of arrivals during the fast-wake mode reaches a threshold, the interface directly wakes up; otherwise, it proceeds to the deep-sleep mode. The sequence of cycles switches between two types: deep-sleep cycles with deep-sleep mode and light-sleep cycles without deep-sleep mode. We analyze the dual-mode strategy based on the condition of the number of arrivals during the fast-wake mode. We first derive the weights of conditions according to the feature of the conditional sleep-mode operation, and then calculate the unconditioned performance measure of the dual-mode strategy based on the weighted average of that of these two kinds of cycles. Finally, we obtain the close-form expressions of the power efficiency and the mean delay, based on which we provide a set of parameter selection rules. We show that the dual-mode strategy with these rules can select suitable sleep modes according to the instantaneous traffic rate, and thus perform well under bursty input traffic.