Abstract
Complex high density VLSI chips (i.e. microprocessors, microcontrollers, and digital signal processors) require packages with V DD /Vssplane(s) and a large number (μ 100) of I/O pins for controlled signal impedance and external communications. However, in typical single layer packages, conductors are metal leadframe connected to the die (chip) with bond wires. Note that single metal layer package does not contain a separate VDD/Vss reference planes, and the current path is confined to the metal lines and bond wires. Typical single layer packages are; 1) PDIP/CDIP (Plastic/Ceramic Dual-InLine Package), PLCC (Plastic Leadless Chip Carrieer, 3) PQFP (Plastic Quad Flat Pack), and 4) CerQUAD (Ceramic Quad Flat Pack). In multi-layer packages, connections from the die to the external world may be through signal traces, bond wires, metal planes, vias, and pins. Vias are used to connect signals from plane-to-plane. Due to these complex VDD /Vss connections at the chip-package interface, modeling “L eff “ (to a single lumped inductance) involves a detailed understanding of the current path through these connections. A software tool describing the current distribution on the VDD/Vss planes is essential to model the reference plane inductance, and thereby the effective inductance ”L eff “.
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