Power Delivery Solutions and PPA Impacts in Micro-Bump and Hybrid-Bonding 3D ICs

Abstract

Face-to-face bonded 3D integration has been shown to provide remarkable performance and power benefits for next-generation computing systems, but power delivery remains a challenge for its applications. In this article, we design industrial-level 3D processors with robust power delivery networks based on two types of 3D integrated circuit (3D IC) fabrication processes, micro-bumping 3D and hybrid-bonding 3D. Considering various process nodes and 3D bonding pitches, we develop a hierarchical physical design flow to build 3D ICs with various power delivery configurations and quantify the impacts of 3D bonding technology on the performance and power integrity. Our experimental results show that fine-pitch hybrid-bonding 3D ICs achieve up to 76% performance improvement or 17-mV IR drop reduction compared with the micro-bump 3D counterparts. Our in-depth analyses on critical paths show that intertier metal sharing is crucial for signal interconnects and power delivery in 3D ICs. In addition, we propose a decoupling capacitance sharing approach based on metal–insulator–metal (MIM) capacitors, which effectively reduces the dynamic voltage drop in micro-bump 3D ICs by up to 77 mV.