Power consumption of 3D networks-on-chips: Modeling and optimization

Abstract

Designing power-efficient Networks-on-Chips (NoCs) for 3D ICs has emerged as a promising solution for complex mobile and portable applications. The total power consumption of a 3D NoC design depends on the allocation of the Intellectual properties (IPs) to the different network routers and the number of Through Silicon Vias (TSVs) used in the design. In this paper, we introduce a new analytical model for the power consumption of 3D NoCs. This new model relies on graph-theoretic concepts and incorporates static and dynamic power in order to present a more accurate evaluation of 3D NoC power consumption. The proposed model utilizes Dijkstra’s algorithm to find shortest path routing. It also reflects the impact of using TSVs in 3D ICs. Using the proposed model, we develop a new methodology to select the 3D NoC topology and find the best IP-mapping. The proposed methodology utilizes a bio-inspired optimization technique. We compare particle swarm optimization (PSO) to genetic algorithms (GAs) in order to find the best 3D mesh network mapping that achieves minimum power consumption. The presented methodology is validated through two case studies to address symmetric and asymmetric multicore applications.