Abstract
The growing demand for portable electronic devices has led to an increased emphasis on power consumption within the semiconductor industry. As a result, designers are now encouraged to consider the impact of their decisions not only on speed and area, but also on power throughout the design space exploration. This article presents a high-level design space exploration methodology. It allows characterising a software application computing on TI-DSPs. The proposed approach exploits parametric models representing the consumption's behaviour of both DSP's architecture and algorithm. This consists in releasing the laws of consumption on a high level. This approach makes it possible to deduce the power and the energy consumption of a code in an advanced language for a given target. Feasibility and the interest of the approach were proved using MPEG2. This new approach was based on a functional level power analysis. The advantage of this approach was that the consumption and performance estimation can be made at a high level. Moreover, the proposed approach gives a detailed function-level characterization of the energy behaviour of application, enabling estimation of software energy consumption.
Highlights
The design of embedded systems on chip is a complex process, involving different steps at different abstraction levels
Design steps can be grouped into two major tasks: architecture design space exploration and selection of architectural platform, parameters components and architecture design
The availability of high performance System on Chip (SoC) devices is an important factor of the electronic market and has attracted significant research interest
Summary
The design of embedded systems on chip is a complex process, involving different steps at different abstraction levels. The overall design process must consider strict requirements, like time to market, system performance, power consumption and cost New applications such as laptop, wireless telecommunications are more and more increasing in the electronic domains. Techniques for synthesis of multiprocessor system architectures and heterogeneous distributed HW/SW architectures for real-time specifications were presented in[13] These approaches either assume that all tasks are pre-characterized with respect to all possible implementations for delay and power consumption, or assume a significantly simplified power dissipation model. The objective of this work is to define an approach of consumption’s estimation in the system level For this reason, we do not propose models of consumption of the target architecture but a model of the algorithms themselves. We do not apply this method to architecture but directly to the algorithm in order to characterize its consumption
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