Power Aware design and Convergence of Router using Unified Power Format Standards

Abstract

The Hardware design verification goal is to check implementation matching with high level specification. Verification process checks the design for agreement with the specifications and reports any discrepancies & bugs. This can be achieved by scripting the assertion coverage to the design. In semiconductor industry power dissipation is a critical issue in most of the System-on-Chips (SOCs) designs. In past, power to any RTL design were made at the physical implementation stages. As on those days total number of cells per chip were lesser. But now a days due to the entire system on chip the number of cells per chip has been increased, So the power implementation cannot be done manually that is by connecting the power pins to the power supplies, so in order to overcome this problem power implementation can be done by introducing the power intent to the design which helps in the reduction of the power. This can be achieved by applying Unified Power Format to the SOCs design and the design power reduction is verified by writing the low power coverage to it. Unified power format is an IEEE 1801 standard format which act as a power intent to any RTL design. VCS is a synopsys tool used for writing the design code and for debugging the code. Assertion coverage results and low power coverage result reports are obtained by generating the report files. This paper explains about the verification by using assertion coverage which helps in early detection of bugs and also reduces the time consumption. Power consumption has been reduced and verified by low power coverage to the design. Both verification and low power coverage has been verified by taking the router as example.