Power - and variability-aware design of FinFET-based XOR circuit at nanoscale regime

Abstract

Escalation in performance parameters due to CMOS technology scaling has proven its worth in the field of design and implementation. Integration density, low power dissipation and higher speed of operation are at their zenith level. This truculent towards technology scaling is now showing its adverse effect which is becoming a great concern from the researchers' point of view. Variability is one of the consequences of technology scaling. Equivalent to power, delay and area, variability also plays an important role in determining performance of circuits. This paper presents variability analysis of diverse exclusive-OR circuits in terms of average power and power-delay product (PDP) at the transistor level using 16-nm technology node. The investigation is supported by using simulation framework loaded with two nominal copies of the analogous XOR gate at both the ends - input and output. The intent of this note is to determine the circuit with minimal variability to PDP. Further, realization of the optimal XOR circuit is carried out by using emerging device namely Fin field effect transistor (FinFET). The propound FinFET based realization of optimal XOR circuit offers 99.191 × improvement in PDP in contrast to its CMOS realization at nominal supply voltage of VDD = 0.7 V.