Power- and performance-aware fine-grained reconfigurable router architecture for NoC

Abstract

Networks-on-Chip (NoCs) have been well accepted for energy efficient on-chip communications for multicore systems. But, a NoC router consumes considerable leakage power even when not in use. For large scale systems, number of unused routers at any time is reasonably high. A significant amount of this leakage power can be saved by applying fine-grained power-gating to unused routers in a NoC. In this paper, we propose fine-grained reconfigurable router architecture (FGRRA) for energy efficient on-chip communications. We also propose strategies to avoid situations where power-gated routers (PGRs) block forward path during packet transfer or isolate a destination router. This is achieved by using additional channels referred as non-blocking bypass channels (NBBC). We evaluate our proposed router design in presence of real and synthetic traffic patterns. FGRRA saves up to 88.76% of leakage power with 2.42% area overhead as compared with baseline router. Based on the utilization, FGRRA also reduces the total network power consumption by 36.18% on average without significant performance degradation. Design considerations for augmenting existing power-gated routers with this technique and corresponding overheads are also presented.