Power and Area Efficient Decimation Filter Architectures of Wireless Receivers

Abstract

This paper reports on the synthesis and implementation of a digital decimation filter suitable for multi-standard transceivers. Decimation filter architectures used in transceivers must be capable of providing low power and less area. In this paper, three different architecture designs namely Decimation Filter with Conventional MAC Unit, Cascaded Multi-Standard decimation Chain and Hybrid structure are proposed to meet the demand of low power and area efficient digital decimation filter. The filter architectures are implemented using FPGA and its performances are tested. The architectures are tested using conventional number system and with two different encoding schemes of filter coefficients called canonic signed digit and minimum signed digit. The implementation results reflect that considerable reduction in area of 47.9 % and power reduction of 28.6 % are achieved using hybrid architecture, when compared with conventional MAC and cascaded chain architectures.