Power analysis of Flash-ADC in 90nm CMOS Technology

Abstract

ADC’s or analog to digital converters are the devices which provide a channel between physical & digital world as they are responsible for converting continuous time analog signal to a digital digit. ADC’s is a prominent component of high speed data communication, signal conditioning & processing applications. So, a power efficientADC is required which will be best suited for these applications. A 4-BIT flash-ADC is simulated in this work in 90 nm CMOS technology. Voltage supply of 0.7 V is applied with 1 μm channel length. Power consumption is then recorded & observed by varying the temperatures at different widths & supply voltages. Minimum power consumption of 11.73 μW at -10degreeCelsius & maximum power consumption of 14.94 μW at 55 degrees Celsius is observed. temperature variation leads to the 25% variations in power consumption. For comparison latest flash-ADC are taken & compared. Comparison shows better performance of this 4-bit flash-ADC from others. Simulations are executed by employing SPICE based on 90 nm CMOS technology.