Power analysis and comparison of clock gated techniques implemented on a 16-bit ALU

Abstract

Power dissipation is a bottleneck in the design of low power electronic devices that, operate at high frequencies. Hence, the clock signal is a major source of power dissipation. The technique clock gating at the architecture level can be implemented to reduce the dynamic and clock power. In this paper, the authors aim at implementing, analyzing and comparing the various resource power using clock gating techniques to a 16-bit ALU on a 45nm SPARTANO FPGA board. The two clocking gates proposed and used in the design are namely: DEMUX and AND gate, which provide clock input to only one functional module that is either arithmetic or logical block, while the other is put OFF. The complete design is simulated using QuestaSim, synthesized using Precision tool and the power analysis is performed using Xpower analyzer of ISE13.2. The results obtained demonstrate that the clock, signal and the logic power for the two techniques is nearly same. While the IO and dynamic power using AND clocking gate has the power reduction of 50% and 45% respectively. Thus, the AND clock gating technique can be used in the design to optimize power and area.