Power amplifier nonlinear modeling for digital predistortion

Abstract

Introduction Nowadays, one of the main common objectives in all Electrical Engineering research areas consists of reducing energy consumption by enhancing power efficiency. It is well known that the power amplifier (PA) is one of the most power hungry devices in radiocommunications. Therefore, to amplify non-constant envelope modulated signals, the use of linear Class-A PAs operating at high-power back-off levels to guarantee the desired linearity is no longer a desirable solution since it results in power inefficiency. In a classical Cartesian I-Q transmitter with static supply, the PA has to linearly amplify a carrier signal which is both phase and amplitude modulated and usually showing high peak-to-average power ratios (PAPRs), which implies that for having linear amplification it is necessary to use extremely inefficient class-A or class-AB PAs. Power amplifier system level linearizers, such as digital predistortion (DPD), extend the linear range of power amplifiers which, properly combined with crest factor reduction (CFR) techniques [1], enable PAs to be driven harder into compression (thus more efficient) while meeting linearity requirements. Thanks to the intensive processing capabilities offered by the “always faster” digital signal processors, some power supply control architectures with great potential for high-efficiency operation have been revived. The PA drain supply modulation is carried out using techniques such as envelope elimination and restoration (EE&R) [2] and envelope tracking (ET) [3],[4] in conjunction with DPD. Therefore, the use of linearizers, and more precisely DPD, becomes an essential solution to mitigate nonlinear distortion effects arising from the use of more efficient but highly nonlinear PAs (Class D, E, F switched PAs) in both Cartesian and Polar transmitter architectures.