Post-Silicon SoC Validation Challenges

Abstract

Modern System-on-Chip (SoC) designs are becoming increasingly complex and powerful to meet the ever-growing computing demands form diverse application domains including the emerging Internet of Things (IoT). Given the widespread acceptance of SoCs in the electronic industry, it is critical to ensure their correctness from both functional and nonfunctional perspectives. SoC design complexity is increasing rapidly keeping pace with twofold increase in number of transistors every technology cycle. Drastic increase in design complexity has led to significant increase in SoC validation complexity. Due to increasing design complexity coupled with shrinking time-to-market constraints, it is not possible to detect all design flaws (errors) during pre-silicon validation. Post-silicon validation needs to capture these escaped functional errors as well as electrical faults including crosstalk, delay, and transient faults. Post-silicon validation is widely acknowledged as a major bottleneck in SoC design methodology—many recent studies suggest that it consumes more than 50% of an SoCs overall design effort (total cost) at 65nm technology. This problem is expected to get worse as the industry continues to move to even smaller geometries. This chapter provides a comprehensive overview of different challenges associated with SoC post-silicon validation and debug.