Post-processing using microfabrication techniques to improve the optical performance of liquid crystal over silicon backplane spatial light modulators

Abstract

Liquid crystal (LC) over silicon backplane spatial light modulators (SLMs) have applications in optical processing and as miniature displays. With these devices a LC layer is sandwiched between the silicon backplane and a front cover glass coated with a transparent ITO electrode. The voltage between electrodes on the controlling circuitry and the ITO electrode determines the state of the LC which in turn is used to modulate incident light onto the device. The silicon backplane consists of an array of pixels similar to DRAM or SRAM devices but where each pixel controls the voltage on an electrode. These electrodes must also act as mirrors reflecting the incident light. The silicon backplanes supplied by commercial foundries which work well electrically suffer from having poor optical quality pixel mirrors. These mirrors have inferior surface quality with low flat fill factor resulting in low optical efficiency. Hillocks are also present which cause problems with LC cell construction. We have developed a post-processing procedure based on silicon microfabrication techniques to add another level of metal to commercially fabricated wafers which addresses these problems. To ensure that his new metal layer is deposited onto a very flat substrate the interlevel dielectric is planarized using chemical mechanical polishing. We have developed this technique to produce an optical quality surface with local surface variations of less than 100 angstrom consistently achieved. The deposited aluminium top layer is optimized for best optical performance within the constraints of the electrical characteristics. Pixel mirrors with flat fill factors up to 84% were realized which improved the optical efficiency of the SLM. No hillocks were present on the metal surface presenting the opportunity to fabricate 1 micrometers thick LC cells to fully utilize the potential of ferroelectric LC. We will also report on a n expansion of the post-processing procedure to protect devices based on DRAM memory layout from photo induced charge leakage. The use of microfabrication techniques to construct the LC spacer layer will also be discussed.