Postprocessing Procedure for Reducing the Faulty Switching Activity of a Low-Power Test Set

Abstract

Low-power test generation procedures reduce the switching activity during functional capture cycles of scan-based tests in order to avoid overtesting of delay faults. The switching activity that these procedures address is the one in the fault-free circuit. Recently it was shown that excessive switching activity in faulty circuits can potentially cause test escapes. To avoid such situations, this paper describes a postprocessing procedure that reduces the switching activity of a low-power test set in faulty circuits. The main challenge that this procedure needs to address is the large number of faulty circuits for which the switching activity may be excessive. This challenge is addressed in this paper by reducing the fault-free switching activity in order to create a safety margin for an increased faulty switching activity. The safety margin is computed for every test individually. Experimental results for benchmark circuits demonstrate the ability of the procedure to eliminate excessive faulty switching activity for low-power test sets.