Abstract

Photonic packaging, which includes high-precision assembly of photonic sub-systems, is currently a bottleneck in the development of commercially-available integrated photonic products. In the pursuit of a fully-automated, high-precision, and cost-effective photonic alignment scheme for two multi-channel photonic chips, this paper explores different designs of the on-chip electrothermal actuators for positioning mechanically-flexible waveguide structures. The final alignment goal is ∼100 nm waveguide to waveguide. The on-chip actuators, particularly for out-of-plane actuation, are built in a 16 μm-thick SiO photonic-material stack with 5 μm-thick poly-Si as an electrothermal element. A major challenge of out-of-plane positioning is a 6 μm height difference of the waveguides to be aligned, due to different built-up material stacks, together with a misalignment tolerance of 1 μm–2 μm from the pre-assembly (flip-chip) process. Therefore, the bimorph-actuator design needs to compensate this height difference, and provide sufficient motion to align the waveguides. We propose to exploit the post-release deformation of so-called short-loop bimorph actuator designs to meet these joint demands. We explore different design variants based on the heater location and the integration of actuator beams with waveguide beams. The actuator design (with 30 μm poly-Si and 900 μm SiO in length) has ∼8 μm out-of-plane deflection and is able to generate ∼4 μm motion, which meets the design goal.

Highlights

  • Photonic integration technology, i.e., the design and microfabrication of on-chip optical functions, is key to establishing advanced applications in, e.g., data communication and sensing

  • This section summarizes the characterization of the various bimorph actuator designs

  • The post-release deformation and motion range of actuator beam arrays are characterized for varying Lpoly on post-release deformation (Section 3.1)

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Summary

Introduction

I.e., the design and microfabrication of on-chip optical functions, is key to establishing advanced applications in, e.g., data communication and sensing. Generic foundry-based processes in the photonic domain have brought PIC costs within the scope of many applications, i.e., ∼e 10–100 per chip [1,3,4]. A key bottleneck for market entrance is volume-compatible integration, i.e., assembling one or more PICs together with other optical and electrical components into a single housing [5]. The standardization of packaging and the automation of assembly processes for photonic products are still in their infancy. The current photonic packaging and assembly technologies are mainly based on custom-engineered solutions, which makes device integration an order of magnitude more expensive than the PIC cost [3]. The fine-alignment of optical components to maximize light coupling is a major challenge

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