Abstract
Compact model extraction of phase-locked loop (PLL) frequency synthesizer using system identification techniques is proposed to reduce post-layout simulation time. This is the first published compact model for PLL using system identification techniques. It features an autoregressive exogenous model for the charge pump and the loop filter with a lookup table for nonlinearity compensation and a radial basis function neural network for the voltage-controlled oscillator with nonlinear frequency-voltage relationship, thereby reducing the post-layout simulation time to 26% of the original circuits with the accuracy of 93%.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
More From: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.