Post-CMOS Fabrication Technology Enabling Simultaneous Fabrication of 3-D Solenoidal Micro-Inductors and Flexible I/Os

Abstract

In this paper, co-fabrication and characterization of micro-inductors with mechanically flexible interconnects (MFIs) as I/Os is presented. A double-lithography and double-reflow process is used to obtain different heights of reflowed photoresist domes for the micro-inductors and the MFIs. The developed process allows fabrication of MFIs with different heights, pitches, and materials. The fine-pitch copper MFIs allow for dense connections between chips using interconnect bridging or stitching technologies (embedded multi-die interconnect bridge, heterogeneous interconnect stitching technology, etc.), while the large nickel tungsten (NiW) MFIs enable connections with the base substrate. The interconnect stitch chip can also host integrated passive devices, allowing close integration with active chips. Furthermore, the stitch chip can be fabricated out of low-loss substrate, enabling high-quality passives along with low-loss electrical interconnections. Copper micro-inductors with two different numbers of turns were fabricated on glass to minimize substrate losses; inductance, resistance, and Q-factor values of 0.45 nH, $4~\Omega $ , and 25 were obtained at 33 GHz for the five-turn inductor with a self-resonant frequency of >40 GHz. The compliance of the fabricated 9- $\mu \text{m}$ -thick Cu MFI was measured to be 1.1 mm/N, while that of the 7- and 10- $\mu \text{m}$ -thick NiW MFIs were measured to be 10 and 2.6 mm/N, respectively.