Abstract
In order to achieve high cleaning efficiency requirement for post Chemical Mechanical Polish (CMP) cleaning in Through Silicon Via (TSV) application due to the aggressive CMP process. More comprehensive wafer defect evaluation techniques are needed to understand the cleaning mechanisms and assist the formulation design process. In this paper, the CSX-T series chemistry is applied to the post CMP cleaning process of various wafer substrates commonly used in TSV integration schemes. The data collected by several techniques are analyzed in detail and compared to demonstrate how and when it can be used in new formulation screening process to ensure good cleaning performance.
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