Positive-bias temperature instability (PBTI) of GaN MOSFETs

Abstract

We have investigated the stability of the gate stack of GaN n-MOSFETs under positive gate stress. Devices with a gate dielectric that consists of pure SiO 2 or a composite SiO 2 /Al 2 O 3 bilayer were studied. Our research has targeted the evolution of threshold voltage (V T ), subthreshold swing (S) and transconductance (g m ) after positive gate voltage stress of different duration at different voltages and temperatures. We have also examined the recovery process after the stress is removed. We have observed positive V T shift (ΔV T ) in both gate dielectrics under positive gate stress. In devices with a SiO 2 gate oxide, we have found that ΔV T is caused by a combination of electron trapping in pre-existing oxide traps and interface trap generation. In devices with a composite SiO 2 /Al 2 O 3 gate oxide, on the other hand, ΔV T is due to electron trapping in pre-existing oxide traps and generation of near interface oxide traps.