Positive gate bias stress-induced hump-effect in elevated-metal metal–oxide thin film transistors**Project supported by the Science and Technology Program of Suzhou City, China (Grant No. SYG201538) and the National Natural Science Foundation of China (Grant No. 61574096).

Abstract

Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium–gallium–zinc oxide thin film transistor, which adopts an elevated-metal metal–oxide structure. As stress time goes by, both the on-state current and the hump shift towards the negative gate-voltage direction. The humps occur at almost the same current levels for devices with different channel widths, which is attributed to the parasitic transistors located at the channel width edges. Therefore, we propose that the positive charges trapped at the backchannel interface cause the negative shift, and the origin of the hump is considered as being due to more positive charges trapped at the edges along the channel width direction. On the other hand, the hump-effect becomes more significant in a short channel device (L = 2 μm). It is proposed that the diffusion of oxygen vacancies takes place from the high concentration source/drain region to the intrinsic channel region.