Positive bias temperature instability in p-type metal-oxide-semiconductor devices with HfSiON/SiO2 gate dielectrics

Abstract

We present a detailed investigation on positive-bias temperature stress (PBTS) induced degradation of nitrided hafnium silicate (HfSiON)/SiO2 gate stack in n+-poly crystalline silicon (polySi) gate p-type metal-oxide-semiconductor (pMOS) devices. The measurement results indicate that gate dielectric degradation is a composite effect of electron trapping in as-fabricated as well as newly generated neutral traps, resulting a significant amount of stress-induced leakage current and generation of surface states at the Si/SiO2 interface. Although, a significant amount of interface states are created during PBTS, the threshold voltage (VT) instability of the HfSiON based pMOS devices is primarily caused by electron trapping and detrapping. It is also shown that PBTS creates both acceptor- and donor-like interface traps via different depassivation mechanisms of the Si3 ≡ SiH bonds at the Si/SiO2 interface in pMOS devices. However, the number of donor-like interface traps ΔNitD is significantly greater than that of acceptor-like interface traps ΔNAit, resulting the PBTS induced net interface traps as donor-like.