Porous Silicon for Chip Cooling Applications

Abstract

Porous silicon (PSi) was prepared by electrochemical etching with electrolytes consisting of various concentrations of HF and dimethylsulphoxide (DMSO) to control the pore size in the range 0.4µm–8µm as measured by scanning electron microscopy. Pool boiling experiments employing resistive heating of samples with a PSi surface in the dielectric cooling liquid FC-72 was performed and compared to samples with a polished Si surface. It was observed that the PSi surface had favorable cooling behavior and yielding the lowest temperature overshoot upon warming up and the lowest surface temperature during boiling by promoting continuous bubble nucleation which again leads to the most efficient heat removal. The results indicate that PSi could favorably be used in cooling of electronic chips. We also present demonstration of the successful fabrication of a Si porous membrane by a onestep electrochemical etching procedure. The onestep etching technique could be used as an alternative method to the standard Si micro machining such as etched by KOH. The PSi membrane could be used for various closed loop two-phase coolers.