Polysilicon Interface Engineering for Improved PIP Capacitors

Abstract

The capacitor module has been a challenge for both extrinsic and intrinsic oxide quality for polysilicon/insulator/polysilicon capacitors integrated into ASIC mixed-signal devices. A change in the process sequence where the bottom polysilicon surface is protected from subsequent processing has been found to greatly improve oxide integrity. However this approach is cost prohibitive for an existing product line, as there are many mission critical, high reliability customers who require extended qualification. Nonetheless, these same customers are driving toward zero defectivity for their existing products. A plasma-based interclean etch inserted between the two wet cleans prior to capacitor oxide deposition was found to substantially improve oxide integrity. The increase in the capacitor linearity as a result of the etch was minimal and was attributed to the removal of a portion of the phosphorus-rich material at the polysilicon surface.