Polyphase Structure with Periodically Time-Varying Coefficients: a Realization for Minimizing Hardware Subject to Computational Speed Constraint

Abstract

It is well known that polyphase realizations of multirate converters reduce the constraint on computational speed of the hardware, namely, the filter is decomposed into several filters which operate at a slower speed. With a slower speed, the speed requirement of hardware is relaxed. The speed reduction depends on the signal conversion rate. However, there is no hardware saving since the amount of hardware is similar to that of the original filter. Recently, periodically time-varying (PTV) structures have been proposed to reduce the hardware of multirate converters. By using each hardware multiplier for realizing several filter coefficients by means of sharing in a periodic manner, we achieve hardware reduction. The amount of hardware reduction depends on the signal conversion rate. However, the processing speed of each multiplier is the same as the that of the original filter. Each of the two techniques above achieve one objective while the other factor is unchanged. We show that by combining the two techniques to obtain a polyphase structure with PTV coefficients, we can obtain both hardware saving and reduction in computation speed requirement. We can trade the hardware saving and the reduction in computation requirement. From the viewpoint that we wish to obtain hardware realization of a multirate converters when the processing speed is limited by the hardware's computation speed, the proposed PTV polyphase structure offers minimum hardware under such limitation. The decimator is used in this paper to demonstrate the idea