Point Defect Kinetics and Extended-Defect Formation during Millisecond Processing of Ion-Implanted Silicon

Abstract

One challenge in successfully scaling the dimensions of the MOSFET transistor is in maintaining a highly activated ultrashallow p-type source/drain extension (p-SDE) region under the gate. Ion implantation introduces significant levels of damage and dopant that is not electrically active into the lattice. The thermal processing necessary to activate this dopant, while also limiting the dopant motion, is evolving. A high-power arc-lamp design has enabled millisecond annealing as an alternative to conventional rapid thermal processing, which operates on the timescale of seconds for ultrashallow junction formation. This chapter summarizes some investigations into the use of millisecond annealing to form a highly activated ultrashallow junction, while simultaneously minimizing diffusion. In order to minimize dopant motion the various mechanisms that lead to diffusion during millisecond annealing are discussed. Examples of how changing the proximity of the damage to the dopant, allow one to understand these mechanisms and the role of annealing temperature are presented. Finally, the mechanisms of postimplantation dopant activation are discussed. It is shown that it is critical to understand the interplay between dopants, point defects, extended defects and processing if one is to understand the evolution of ultrashallow p-type junctions.