POGO PIN PARASITIC IMPEDANCE CHARACTERISATION AND INFLUENCE ON PMIC SEMICONDUCTOR EVALUATION PROCES

Abstract

During the semiconductor evaluation of modern Power Management Integrated Circuit (PMIC) devices, high quality Zero-Insertion-Force (ZIF) sockets must be used in order to measure many semiconductor parts with a single dedicated hardware. The most critical part of socket is contact between the device terminal and PCB. There are couples of technology processes that can provide solid contact between the device and the rest of the circuit, but the most common technology uses so called Pogo-pin, also called spring pin. Pogo pin must have as small as possible parasitic impedance, since the signal frequency and the signal power transfer between the PMIC terminal and the rest of the circuit must be without distortions, in order to obtain correct measurement results of tested devices. In some cases, influence of Pogo-pin parasitic impedance can lead to the partial damage of the device internal structure. This article should point to the potential problems using simulation results and should describe the simple procedure of Pogo-pin impedance characterization using network analyzer with appropriate aperture. Couples of measurements results from different Pogo-pin suppliers are also shown in this example with some practical results.