Abstract
An m-sequence (PN sequence) preestimator scheme for direct-sequence spread spectrum (DS-SS) signal acquisition by using block sequence estimation (BSE) is proposed and analyzed. The proposed scheme consists of an estimator and a verifier which work according to the PN sequence chip clock, and provides not only the enhanced chip estimates with a threshold decision logic and one-chip error correction among the first m received chips, but also the reliability check of the estimates with additional decision logic. The probabilities of the estimator and verifier operations are calculated. With these results, the detection, the false alarm, and the missing probabilities of the proposed scheme are derived. In addition, using a signal flow graph, the average acquisition time is calculated. The proposed scheme can be used as a preestimator and easily implemented by changing the internal signal path of a generally used digital matched filter (DMF) correlator or any other correlator that has a lot of sampling data memories for sampled PN sequence. The numerical results show rapid acquisition performance in a relatively good CNR.
Highlights
PN sequence acquisition is a precondition for stable and reliable spread spectrum communication
We propose a preestimator scheme that can cooperate with a digital matched filter (DMF) correlator for PN sequence acquisition sharing the unused elements of the DMF structure within a given period of time, and can analyze its performance
For the numerical calculations derived in the previous sections, the register length m of the linear feedback shift register (LFSR) PN sequence generator is 15
Summary
PN sequence acquisition is a precondition for stable and reliable spread spectrum communication. We propose a preestimator scheme that can cooperate with a DMF correlator for PN sequence acquisition sharing the unused elements of the DMF structure within a given period of time (filling up the time of the DMF registers with the sampled PN chips or the given fixed operation time limits), and can analyze its performance. This scheme provides one-chip error correction capability of the initially loaded PN sequence chips on the LFSRs and a flexibility to manage structural resources of a correlator structure.
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