Abstract
Local SiGe layer thickening next to spacers in the embedded planar Si pMOS transistors showing an improved performance comparing to Si reference was found. Such SiGe growth behavior was simulated using a mask with different window sizes and studied by various techniques. It was found that although Nomarski spectroscopy shows a decrease of misfit dislocations linear density with window size shrinkage, suggesting perfectly strained layers, high resolution X-ray diffraction (HRXRD) and Raman investigations show a dramatic increase of relaxation for windows smaller than 5 × 5 μm 2 for all investigated samples. It is suggested that this is because of local thickening at the window edges (similar to thickening next to spacers in devices), which is due to elastic relaxation caused by the convex corners of the recessed areas.
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