Abstract
In this brief, a pMOS pass gate (PPG) local bitline static random access memory (LB SRAM) architecture is proposed to reduce the read delay and resolve the half-select issue with a small area overhead. Virtual $V_{\mathrm {SS}}$ write assist is included in the architecture to improve write ability. In 22-nm fin-shaped FET (FinFET) technology, the proposed PPG LB architecture achieves an improved read delay and reduced total operation energy by 44% and 65%, respectively, at 0.4 V, compared to the full-swing LB (FSLB) SRAM architecture.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
More From: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.