Plug N’ PIM: An integration strategy for Processing-in-Memory accelerators

Abstract

Processing-in-Memory (PIM) devices have reemerged as a promise to mitigate the memory-wall and the limitations of transferring massive amount of data from main memories to the host processors. Novel memory technologies and the advent of 3D-stacked integration have provided means to compute data in-memory, either by exploring the inherent analog capabilities or by tight-coupling logic and memory. However, allowing the effective use of a PIM device demands significant and costly modifications on the host processor to support instructions offloading, cache coherence, virtual memory management, and communication between different PIM instances. This paper tackles these challenges by presenting a set of solutions to couple host and PIM with no modifications at host side. Moreover, we highlight the limitations presented on modern host processors that may prevent full performance extraction of the PIM devices. This work presents Plug N’ PIM, a set of strategies and procedures to seamlessly couple host general-purpose processors and PIM devices. We show that with our techniques one can exploit the benefits of a PIM device with seamless integration between host and PIM, bypassing possible limitations on the host side.