PLL-based electrical balance CMOS integrated duplexer with hybrid transformer

Abstract

This paper describes the design of an integrated duplexer with electrical balance network using the phase locked loop (PLL) for impedance variation tracking. The hybrid transformer is devised for blocking the transmitted signal leaking to the receiver. We suggest a method of impedance tracking based on PLL system, which can maintain high isolation between the transmitter and the receiver. The PLL is employed to sense the transmitter leakage continuously and tune the impedance of the electrical balance network adaptively in real time. The isolation between the transmitter and the receiver is maintained almost constantly in a range of capacitances used in the antenna model, compared with that without the phase locked loop. The return loss at the transmitter port and the insertion loss from the transmitter to the antenna port are measured 30 dB and 6.9 dB at 1.95 GHz, respectively. The planar inverted-F antenna (PIFA) model is used for simulating and measuring antenna and electrical balance network. A capacitor value comprising the PIFA is varied and the proposed duplexer is investigated, leading to automatic impedance tracking in some range.