PLL phase margin design and analysis for mitigating sub/super-synchronous oscillation of grid-connected inverter under weak grid

Abstract

Under weak grid, the grid-connected inverter can easily cause sub/super-synchronous oscillations, which are determined by the oscillation modes of system. Firstly, based on the eigenvalue analysis, the sub/super-synchronous oscillation modes of the grid-connected inverter are revealed with considering the phase-locked loop (PLL) and control delay. With the decline of grid stiffness, the typical roots of sub-synchronous oscillation (SSO) mode gradually shift from the left-half plane to the right-half plane, which means that the grid-connected inverter will oscillate under weak grid. By analyzing the participation factor of SSO mode, it finds that PLL is the dominant factor. Based on the root locus analysis, the stable regions of PLL parameter are obtained. Then, according to the stable regions of PLL parameter, the phase margin of PLL can be calculated, which can make the grid-connected inverter operate stably. It finds that PLL phase margin should be increased for suppressing this SSO. However, when the PLL phase margin is greater than a certain value, the system will enter a supersynchronous oscillation mode, which can cause a supersynchronous oscillation. Thus, to suppress the sub/super-synchronous oscillations of the grid-connected inverter under weak grid, the phase margin of PLL should neither be too small nor too large. Finally, the proposed suppression strategy of the sub/super-synchronous oscillations for the inverter integrated into a weak grid is validated with the simulation and experimental studies.