Plasma protection module design for ITER CIS fast architecture

Abstract

The ITER central interlock system (CIS) architecture is composed of four categories of hardware: the fast architecture, slow programmable logic controller (PLC)-based architecture, hardwired architecture, and servers. The CIS fast architecture receives interlock events from various local plant systems of ITER and communicates the corresponding actions to any other local plant systems in order to avoid or mitigate the damage to the machine. Such functions require a reaction time in the range of 1–10ms, which is faster than the capability of a PLC. The CIS fast architecture consists of a module called the plasma protection module (PPM), which is mainly in charge of interlock functions related to the plasma. In addition to satisfying the time performance requirements, the PPM complies with the CIS reliability, availability, and integrity requirements (a probability of failure per hour of less than 10E-7 and a failsafe solution). In this paper, we explain the engineering design of our approach from a technical perspective. A COTS FPGA in a redundant configuration solution, which uses serial communication with the local plant systems, is considered.