Plasma process-induced damage on thick (6.8 nm) and thin (3.5 nm) gate oxide: parametric shifts, hot-carrier response, and dielectric integrity degradation

Abstract

It is shown that the primary manifestation of charging damage in thin (<4 nm) oxides is a degradation of dielectric integrity, while the primary manifestation of damage in thick (>6 nm) oxides is a shift in threshold voltage and/or the degradation of hot-carrier immunity. It is therefore necessary to monitor both dielectric integrity and parametric shifts to determine the consequences of charging damage on a technology with multiple gate oxide thicknesses. We demonstrate the efficacy of a ramp breakdown methodology for measuring dielectric integrity, showing that a simple measurement of current is not sufficiently sensitive, and that results equivalent to a lengthy time-to-breakdown test may be achieved. We describe a highly accelerated hot-carrier stress for monitoring damage on thicker oxide and show how it illuminates latent damage and is superior to Fowler–Nordheim stressing for this purpose. Furthermore, we show data on some thousands of chips from a manufacturing line, which demonstrates robust charging behavior for realistic gate and wiring antennas.