Abstract
The liquid phase chemical enhanced oxidation (LPCEO) technique was applied to achieve planarized isolation of a high-indium-content In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.52</sub> Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.48</sub> As/In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.8</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.2</sub> As metamorphic high-electron-mobility transistor (MHEMT). Through a simple, low-temperature process not requiring costly machinery, electrical isolation of components was accomplished. In addition, multiple advantages were gained, including the production of planarized surfaces, low pollution, and reduction in the subsequent disposal of wet etching solution and costs for dry etching or ion implantation. Because of the decrease in lateral defect density caused by wet or dry etching and the further decrease in gate leakage current owing to the isolated oxide film, the performance of devices, with improved DC characteristics, less flicker noise, and enhanced high-frequency performance, can be increased.
Highlights
In the gallium arsenide (GaAs) integrated circuits (ICs) fabrication process, electrical isolation is necessary to reduce gate leakage current between components
The surfaces of isolation regions produced using wet or dry etching are excessively heterogeneous in height, which is unfavorable for improving the photolithography resolution and reliability of metal interconnects
ION is defined as IDS at VGS equals threshold voltage+0.5 V, and IOFF is defined as IDS at VGS equals threshold voltage−0.5 V. These results reveal that the liquid phase chemical enhanced oxidation (LPCEO) isolation can suppress SS through reducing the surface recombination current of LPCEO-grown oxide near the isolated sidewall of the mesa
Summary
In the gallium arsenide (GaAs) integrated circuits (ICs) fabrication process, electrical isolation is necessary to reduce gate leakage current between components. To achieve a superior isolation effect, electrical insulating materials are typically adopted to space the components at specific distances. Wu et al [10] performed substrate isolation by employing a GaAs MOS field effect transistor (MOSFET) and compared the effects of the no isolation process, mesa isolation, and planar oxide isolation. Their experimental results revealed that ohmic resistance at the two ends after insulation was 106 times higher than that before isolation, and the effect of planar oxide isolation was comparable to that of mesa isolation. Without mesa etching and by performing direct
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
