Planarized Copper Interconnects by Selective Electroless Plating

Abstract

ABSTRACTElectroless deposition of planarized copper in SiO2 trenches has been carried out using Pd/Si plasma immersion ion implantation (PIII) or Pd2Si deposition to form a seed layer at the bottom of trenches. Electrical resistivity of the plated Cu is < 2 μΩ-cm for both types of seeding layers. For the PHI seeding method, we found a threshold Pd dose of 2 ×l014/cm2 is required to initiate Cu plating, and RBS analysis confirms intermixing of Pd, Si, and SiO2 improves the adhesion of the plated Cu to SiO2. Electromigration tests show both void and hillock formation under accelerated current stress testing, with an activation energy of 0.8 eV for interconnect open failure. The DC and pulse-DC median-time-to-failure (MTF) of plated Cu are found to be about two orders of magnitude longer than that of Al-2%Si at 275°C, and about four orders of magnitude longer than that of Al-2%Si when extrapolated to room temperature. Pulsed DC electromigration stressing exhibits a transition from low to high frequency behavior around 900 kHz, indicating a vacancy relaxation time much shorter than that of Al. For bipolar AC stressing, the ratio MTFAC / MTFDC of Cu is much smaller than that of Al-2%Si, indicating a different void recovery mechanism for Cu.