Planar edge terminations for high voltage 4H-SiC power MOSFETs

Abstract

Several edge termination structures for high voltage 4H-SiC devices compatible with a planar power MOSFET fabrication process are analyzed in this paper. The edge terminations’ efficiency has been experimentally demonstrated on PiN diodes with breakdown voltage capabilities ranging from 2 to 5 kV, fabricated within a full power MOSFET process technology. The studied edge terminations consist of typical JTEs, novel FGRs using MOSFET P-well implantation, as well as a combination of JTEs and FGRs. The experimental results have shown a good efficiency of most of the implemented edge terminations. It is also shown that P-well FGRs could be an effective cost solution for high voltage SiC based power MOSFETs. Moreover, the edge termination combining JTEs and FGRs concepts shows a better tolerance of breakdown voltage values against variations in the JTE dose. The same edge termination design allows one to obtain a good efficiency for both 1.7 and 4.5 kV PiN diodes. The optimal termination has been successfully implemented on 4.5 kV power MOSFETs.