Planar cmos compatible process for the fabrication of buried microchannels in silicon, using porous-silicon technology

Abstract

This work presents a new method for the fabrication of buried microchannels, covered with porous silicon (PS). The specific method is a two-step electrochemical process, which combines PS formation and electropolishing. In a first step a PS layer with a specific depth is created at a predefined area and in the following step a cavity underneath is formed, by electropolishing of silicon. The shape of the microchannel is semi-cylindrical due to isotropic formation. The method allows accurate control of the dimensions of both PS and the cavity. The formation conditions of the PS layer and the cavity were optimized so as to obtain smooth microchannel walls. In order to obtain stable structures the area underneath the PS masking layer was transformed into n-type by implantation, taking advantage of the selectivity of PS formation between n- and p-type silicon. With this technique, a monocrystalline support for the PS layer is formed on top of the cavity. Various microchannel diameters with different thickness of capping PS layer were obtained. The process is CMOS compatible and it uses only one lithographic step and leaves the surface of the wafer unaffected for further processing. A microfluidic thermal flow sensor was fabricated using this technology, the experimental evaluation of which is in progress.