Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion

Abstract

VLSI implementation of Cellular Automata (CAs) has gained importance owing to its features which guarantee parallelism, locality and structural regularity. In this work, we have addressed the design challenges pertaining to an implementation optimized for speed, of tree-structured linear CA architectures on Field Programmable Gate Array (FPGA) with built-in scan paths. Scan based design facilitates state initialization, helps to escape from any graveyard state, or figure out faulty locations (if any) on which the circuit is mapped. Our design automation platform generates synthesizable circuit descriptions of tree-structured CA on FPGA, and appends scan functionality without additional logic or speed overhead. Placement algorithms governing the map of CA cell nodes on the FPGA slices have been proposed to ensure maximum physical proximity among CA cells sharing neighborhood dependencies. This is done to exploit the VLSI amenable features such as physical adjacency of the neighboring nodes participating in the next state (NS) computation of each other. The ultimate implementation leads to minimum spacing of linear order between CA neighbours. The NS logic of each CA cell inclusive of scan multiplexing, owing to restricted neighborhood size, is realized using a single Look-Up Table. Our architectures outperform behavioral implementations realized with higher levels of design style abstraction.