Abstract
A graph-partitioning-based PLA (programmable logic array) folding algorithm is described. It is solved as a row/column reordering problem by following the approach of F.H. Wang et al. (1987). The implementation considers the area of the folded PLA as the cost function. Many experimental results show that the tool produces results superior to those produced by the PLEASURE program. The results are also about as good as those produced by a simulated-annealing-based algorithm. >
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