Pipelining flat CORDIC-based trigonometric function generators

Abstract

The significant advances in VLSI technology provided the impetus for porting algorithms into architectures. The CORDIC algorithm reigned supreme in this regard due to its canny ability to decimate trigonometric and hyperbolic functions with simple shift and add operations. Despite further refinements of the algorithm with the introduction of redundant arithmetic and higher radix CORDIC techniques, in terms of circuit latency and performance, the iterative nature remains to be the major bottleneck for further optimization. Although several techniques have been prosed to minimize this drawback, a technique known as flat CORDIC aims to eliminate it completely. In flat CORDIC, the conventional X and Y recurrences are successively substituted to express the final vectors in terms of the initial paper, the techniques devised for the VLSI efficient implementation of a 16-bit flat CORDIC based sine-cosine generator are presented. Three schemes for pipelining the 16-bit flat CORDIC design for high throughput solutions have been discussed. The 16-bit architecture has been synthesized using 0.35(mu) CMOS process library. Finally, a detailed comparison with other major contributions show that the flat CORDIC based size-cosine generators are, on an average, 30 percent faster with a significant 30 percent saving in silicon area.