Pipelined photonic analog-to-digital converter

S R Abdollahi,T J Owens,H S Al-Raweshidy

doi:10.1088/2040-8986/aad922

Abstract

Electronic analog to digital converters (EADCs) face serious challenges when the root mean square timing jitter of the sampling pulse is less than a femtosecond. This restriction limits the maximum allowable sampling frequency of an EADC. In photonic analog-to-digital conversion (PADC), using a mode locked laser as a sampling source limits the sampling frequency timing jitter only at sub-femtosecond levels. The current architectures for PADC use photonic techniques either for sampling or for quantization. Consequently, current PADC architectures are not suitable for higher frequency applications because of the limitations of their electronic components. In this paper, the feasibility of implementing concept architecture for a fully photonic pipelined ADC is analyzed and evaluated to provide a design for an 8-bit pipelined PADC, the performance of which is investigated through modeling and simulation. The 8-bit pipelined PADC’s effective number of bits is shown to be 4.34 bits at 200 gigasample per second.

Highlights

Digital systems achieve a better dynamic range than analog systems, and more appropriately interface with other systems [1], are flexible, more reliable and robust against additive noise
In the successive approximation register (SAR) electronic analog-to-digital converters (ADCs) (EADCs) scheme, the sampling rate must be lower than the internal clock frequency, which is the key disadvantage of the SAR EADC architecture
An 8-bit photonic analog-to-digital conversion (PADC) is based on the concept architecture that was discussed in section 2 is evaluated

Summary

Introduction

Digital systems achieve a better dynamic range than analog systems, and more appropriately interface with other systems [1], are flexible, more reliable and robust against additive noise. In photonic assisted ADC architecture, an RF signal is modulated onto an optical carrier; an ultra-stable MLL source switches an electronic track and hold circuit The advantages of these systems are: (a) reduced aperture time, (b) high clock isolation, (c) low clock jitter, (d) optical clock distribution, [7,8,9,10,11,12,13]. In PSEQ techniques, an MLL may be used to sample an electronic representation of an RF signal and quantization is performed using a single high rate EADC, [14,15,16], this system is a photonic assisted EADC.

All-photonic pipelined ADC concept architecture

The proposed pipelined PADC architecture

Discussion of the PADC functionality and performance

Conclusions