Abstract
Presented is a low-power small-area pipelined phase accumulator (PACC) for direct digital frequency synthesisers (DDFSs). To minimise the number of pre-skewing flip-flops, the proposed scheme sequentially loads Frequency Control Word (FCW) input data directly to the corresponding unit accumulators without through series of flip-flops, thus reducing the power consumption as well as the chip area compared to previously reported PACCs. A 24-bit PACC using the proposed scheme is fabricated in a 0.13 µm CMOS process with built-in phase-to-amplitude mapping circuitry and a D/A converter for measurements of the PACC performance. Experimental results show that the proposed architecture reduces power consumption by 21 and 34% compared to CML-based and static CMOS-based conventional PACC designs, respectively.
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