Pipelined hierarchical architecture for high performance packet classification

Abstract

Hierarchical search structures satisfying good memory and update performance demands, are encouraging solution for packet classification in multi-core processors. However, pipelined hardware implementation of these algorithms has two major issues: (1) backtracking which causes stalling the pipeline and (2) memory inefficiency owing to variation in the size of trie nodes. In this paper, we present a clustering algorithm named recursive leaf extraction (RLE) that partitions an input ruleset into a certain number of sub-rulesets to eradicate backtracking in hierarchical search structures. We further enhanced RLE method and proposed Optimized-RLE (O-RLE) algorithm to balance the size of clusters. Additionally, we present a ternary trie data structure (Tϵ) that takes the advantage of ϵ-branch property to segment large trie nodes into fixed size ϵ-nodes to solve the memory inefficiency problem. We propose two hierarchical data structures denoted Tree-Trieϵ (TTϵ) and its extended version Tree-Trieϵ-Linked List (TTϵL). TTϵ consists of a binary search tree in Stage 1 and multiple Tϵ structures in Stage 2. TTϵL comprises an additional linked-list (LL) data structure in Stage 3 that maintains the large portion of ϵ nodes and thus freely optimizes search delay with a significant improvement in memory efficiency (20.39 bytes/rule). To accommodate the proposed data structures, we designed high throughput SRAM-based parallel and pipelined architectures on Field Programmable Gate Arrays (FPGAs) (134 Gbps).